# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=thumbv7-none-eabi -mcpu=cortex-m7 -O3 -run-pass=tbaa,pipeliner %s -o - | FileCheck %s

--- |
  ; ModuleID = 'test.ll'
  source_filename = "test.ll"
  target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
  target triple = "thumbv7m-none-unknown-eabi"

  %struct.bar = type { i16, i16, i16, i16, i16, i16, i16, i16 }

  @bar = external local_unnamed_addr global [0 x %struct.bar], align 2

  define i32 @foo() local_unnamed_addr #0 {
  entry:
    br label %do.body

  do.body:                                          ; preds = %do.body, %entry
    %lsr.iv = phi ptr [ %uglygep, %do.body ], [ getelementptr (i8, ptr @bar, i32 -16), %entry ]
    %count.0 = phi i32 [ 0, %entry ], [ %count.4, %do.body ]
    %uglygep1 = getelementptr i8, ptr %lsr.iv, i32 16
    %0 = load i16, ptr %uglygep1, align 2, !tbaa !0
    %conv = sext i16 %0 to i32
    %uglygep2 = getelementptr i8, ptr %uglygep1, i32 2
    %1 = load i16, ptr %uglygep2, align 2, !tbaa !5
    %conv2 = sext i16 %1 to i32
    %conv.frozen = freeze i32 %conv
    %conv2.frozen = freeze i32 %conv2
    %div = sdiv i32 %conv.frozen, %conv2.frozen
    %conv3 = trunc i32 %div to i16
    %2 = zext i16 %conv3 to i32
    %uglygep3 = getelementptr i8, ptr %uglygep1, i32 12
    %3 = trunc i32 %2 to i16
    store i16 %3, ptr %uglygep3, align 2, !tbaa !6
    %4 = mul i32 %div, %conv2.frozen
    %rem.decomposed = sub i32 %conv.frozen, %4
    %conv8 = trunc i32 %rem.decomposed to i16
    %5 = zext i16 %conv8 to i32
    %uglygep4 = getelementptr i8, ptr %uglygep1, i32 14
    %6 = trunc i32 %5 to i16
    store i16 %6, ptr %uglygep4, align 2, !tbaa !7
    %uglygep5 = getelementptr i8, ptr %uglygep1, i32 4
    %7 = load i16, ptr %uglygep5, align 2, !tbaa !8
    %8 = zext i16 %7 to i32
    %cmp.not = icmp ne i32 %8, %2
    %inc = zext i1 %cmp.not to i32
    %spec.select = add nsw i32 %count.0, %inc
    %uglygep6 = getelementptr i8, ptr %uglygep1, i32 6
    %9 = load i16, ptr %uglygep6, align 2, !tbaa !9
    %10 = zext i16 %9 to i32
    %cmp16.not = icmp ne i32 %10, %5
    %inc19 = zext i1 %cmp16.not to i32
    %count.2 = add nsw i32 %spec.select, %inc19
    %uglygep7 = getelementptr i8, ptr %uglygep1, i32 8
    %11 = load i16, ptr %uglygep7, align 2, !tbaa !10
    %12 = zext i16 %11 to i32
    %cmp24.not = icmp ne i32 %12, %2
    %inc27 = zext i1 %cmp24.not to i32
    %count.3 = add nsw i32 %count.2, %inc27
    %uglygep8 = getelementptr i8, ptr %uglygep1, i32 10
    %13 = load i16, ptr %uglygep8, align 2, !tbaa !11
    %14 = zext i16 %13 to i32
    %cmp32.not = icmp ne i32 %14, %5
    %inc35 = zext i1 %cmp32.not to i32
    %count.4 = add nsw i32 %count.3, %inc35
    %uglygep9 = getelementptr i8, ptr %uglygep1, i32 18
    %15 = load i16, ptr %uglygep9, align 2, !tbaa !5
    %tobool.not = icmp eq i16 %15, 0
    %uglygep = getelementptr i8, ptr %lsr.iv, i32 16
    br i1 %tobool.not, label %do.end, label %do.body

  do.end:                                           ; preds = %do.body
    ret i32 %count.4
  }

  attributes #0 = { "target-cpu"="cortex-m7" }

  !0 = !{!1, !2, i64 0}
  !1 = !{!"bar", !2, i64 0, !2, i64 2, !2, i64 4, !2, i64 6, !2, i64 8, !2, i64 10, !2, i64 12, !2, i64 14}
  !2 = !{!"short", !3, i64 0}
  !3 = !{!"omnipotent char", !4, i64 0}
  !4 = !{!"Simple C/C++ TBAA"}
  !5 = !{!1, !2, i64 2}
  !6 = !{!1, !2, i64 12}
  !7 = !{!1, !2, i64 14}
  !8 = !{!1, !2, i64 4}
  !9 = !{!1, !2, i64 6}
  !10 = !{!1, !2, i64 8}
  !11 = !{!1, !2, i64 10}

...
---
name:            foo
alignment:       2
exposesReturnsTwice: false
legalized:       false
regBankSelected: false
selected:        false
failedISel:      false
tracksRegLiveness: true
hasWinCFI:       false
callsEHReturn:   false
callsUnwindInit: false
hasEHCatchret:   false
hasEHScopes:     false
hasEHFunclets:   false
failsVerification: false
tracksDebugUserValues: false
registers:
  - { id: 0, class: gpr, preferred-register: '' }
  - { id: 1, class: rgpr, preferred-register: '' }
  - { id: 2, class: gpr, preferred-register: '' }
  - { id: 3, class: gpr, preferred-register: '' }
  - { id: 4, class: gpr, preferred-register: '' }
  - { id: 5, class: gpr, preferred-register: '' }
  - { id: 6, class: rgpr, preferred-register: '' }
  - { id: 7, class: rgpr, preferred-register: '' }
  - { id: 8, class: rgpr, preferred-register: '' }
  - { id: 9, class: rgpr, preferred-register: '' }
  - { id: 10, class: rgpr, preferred-register: '' }
  - { id: 11, class: rgpr, preferred-register: '' }
  - { id: 12, class: rgpr, preferred-register: '' }
  - { id: 13, class: rgpr, preferred-register: '' }
  - { id: 14, class: rgpr, preferred-register: '' }
  - { id: 15, class: rgpr, preferred-register: '' }
  - { id: 16, class: rgpr, preferred-register: '' }
  - { id: 17, class: gprnopc, preferred-register: '' }
  - { id: 18, class: rgpr, preferred-register: '' }
  - { id: 19, class: rgpr, preferred-register: '' }
  - { id: 20, class: gprnopc, preferred-register: '' }
  - { id: 21, class: rgpr, preferred-register: '' }
  - { id: 22, class: rgpr, preferred-register: '' }
  - { id: 23, class: gprnopc, preferred-register: '' }
  - { id: 24, class: rgpr, preferred-register: '' }
  - { id: 25, class: rgpr, preferred-register: '' }
  - { id: 26, class: gprnopc, preferred-register: '' }
  - { id: 27, class: rgpr, preferred-register: '' }
  - { id: 28, class: rgpr, preferred-register: '' }
  - { id: 29, class: gprnopc, preferred-register: '' }
liveins:         []
frameInfo:
  isFrameAddressTaken: false
  isReturnAddressTaken: false
  hasStackMap:     false
  hasPatchPoint:   false
  stackSize:       0
  offsetAdjustment: 0
  maxAlignment:    1
  adjustsStack:    false
  hasCalls:        false
  stackProtector:  ''
  functionContext: ''
  maxCallFrameSize: 0
  cvBytesOfCalleeSavedRegisters: 0
  hasOpaqueSPAdjustment: false
  hasVAStart:      false
  hasMustTailInVarArgFunc: false
  hasTailCall:     false
  localFrameSize:  0
  savePoint:       ''
  restorePoint:    ''
fixedStack:      []
stack:           []
callSites:       []
debugValueSubstitutions: []
constants:       []
machineFunctionInfo: {}
body:             |
  ; CHECK-LABEL: name: foo
  ; CHECK: bb.0.entry:
  ; CHECK-NEXT:   successors: %bb.3(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[t2MOVi32imm:%[0-9]+]]:rgpr = t2MOVi32imm @bar
  ; CHECK-NEXT:   [[t2SUBri:%[0-9]+]]:rgpr = t2SUBri [[t2MOVi32imm]], 16, 14 /* CC::al */, $noreg, $noreg
  ; CHECK-NEXT:   [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:rgpr = COPY [[t2MOVi]]
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr = COPY [[t2SUBri]]
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.3.do.body:
  ; CHECK-NEXT:   successors: %bb.4(0x80000000), %bb.5(0x00000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[t2LDRSH_PRE:%[0-9]+]]:rgpr, [[t2LDRSH_PRE1:%[0-9]+]]:gpr = t2LDRSH_PRE [[COPY1]], 16, 14 /* CC::al */, $noreg :: (load (s16) from %ir.uglygep1, !tbaa !0)
  ; CHECK-NEXT:   [[t2LDRSHi12_:%[0-9]+]]:rgpr = t2LDRSHi12 [[t2LDRSH_PRE1]], 2, 14 /* CC::al */, $noreg :: (load (s16) from %ir.uglygep2, !tbaa !5)
  ; CHECK-NEXT:   [[t2SDIV:%[0-9]+]]:rgpr = t2SDIV [[t2LDRSH_PRE]], [[t2LDRSHi12_]], 14 /* CC::al */, $noreg
  ; CHECK-NEXT:   [[t2UXTH:%[0-9]+]]:rgpr = t2UXTH [[t2SDIV]], 0, 14 /* CC::al */, $noreg
  ; CHECK-NEXT:   [[t2MLS:%[0-9]+]]:rgpr = t2MLS [[t2SDIV]], [[t2LDRSHi12_]], [[t2LDRSH_PRE]], 14 /* CC::al */, $noreg
  ; CHECK-NEXT:   [[t2UXTH1:%[0-9]+]]:rgpr = t2UXTH [[t2MLS]], 0, 14 /* CC::al */, $noreg
  ; CHECK-NEXT:   t2STRHi12 [[t2MLS]], [[t2LDRSH_PRE1]], 14, 14 /* CC::al */, $noreg :: (store (s16) into %ir.uglygep4, !tbaa !7)
  ; CHECK-NEXT:   [[t2LDRHi12_:%[0-9]+]]:gprnopc = t2LDRHi12 [[t2LDRSH_PRE1]], 4, 14 /* CC::al */, $noreg :: (load (s16) from %ir.uglygep5, !tbaa !8)
  ; CHECK-NEXT:   t2CMPrr [[t2LDRHi12_]], [[t2UXTH]], 14 /* CC::al */, $noreg, implicit-def $cpsr
  ; CHECK-NEXT:   [[t2ADDri:%[0-9]+]]:rgpr = t2ADDri [[COPY]], 1, 1 /* CC::ne */, $cpsr, $noreg, implicit [[COPY]](tied-def 0)
  ; CHECK-NEXT:   [[t2LDRHi12_1:%[0-9]+]]:gprnopc = t2LDRHi12 [[t2LDRSH_PRE1]], 6, 14 /* CC::al */, $noreg :: (load (s16) from %ir.uglygep6, !tbaa !9)
  ; CHECK-NEXT:   t2CMPrr [[t2LDRHi12_1]], [[t2UXTH1]], 14 /* CC::al */, $noreg, implicit-def $cpsr
  ; CHECK-NEXT:   [[t2ADDri1:%[0-9]+]]:rgpr = t2ADDri [[t2ADDri]], 1, 1 /* CC::ne */, $cpsr, $noreg, implicit [[t2ADDri]](tied-def 0)
  ; CHECK-NEXT:   [[t2LDRHi12_2:%[0-9]+]]:gprnopc = t2LDRHi12 [[t2LDRSH_PRE1]], 8, 14 /* CC::al */, $noreg :: (load (s16) from %ir.uglygep7, !tbaa !10)
  ; CHECK-NEXT:   t2CMPrr [[t2LDRHi12_2]], [[t2UXTH]], 14 /* CC::al */, $noreg, implicit-def $cpsr
  ; CHECK-NEXT:   [[t2ADDri2:%[0-9]+]]:rgpr = t2ADDri [[t2ADDri1]], 1, 1 /* CC::ne */, $cpsr, $noreg, implicit [[t2ADDri1]](tied-def 0)
  ; CHECK-NEXT:   [[t2LDRHi12_3:%[0-9]+]]:gprnopc = t2LDRHi12 [[t2LDRSH_PRE1]], 10, 14 /* CC::al */, $noreg :: (load (s16) from %ir.uglygep8, !tbaa !11)
  ; CHECK-NEXT:   t2CMPrr [[t2LDRHi12_3]], [[t2UXTH1]], 14 /* CC::al */, $noreg, implicit-def $cpsr
  ; CHECK-NEXT:   [[t2ADDri3:%[0-9]+]]:rgpr = t2ADDri [[t2ADDri2]], 1, 1 /* CC::ne */, $cpsr, $noreg, implicit [[t2ADDri2]](tied-def 0)
  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:gpr = COPY [[t2ADDri3]]
  ; CHECK-NEXT:   [[t2LDRHi12_4:%[0-9]+]]:gprnopc = t2LDRHi12 [[t2LDRSH_PRE1]], 18, 14 /* CC::al */, $noreg :: (load (s16) from %ir.uglygep9, !tbaa !5)
  ; CHECK-NEXT:   t2CMPri [[t2LDRHi12_4]], 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
  ; CHECK-NEXT:   t2Bcc %bb.5, 0 /* CC::eq */, $cpsr
  ; CHECK-NEXT:   t2B %bb.4, 14 /* CC::al */, $noreg
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.4.do.body:
  ; CHECK-NEXT:   successors: %bb.5(0x04000000), %bb.4(0x7c000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[PHI:%[0-9]+]]:gpr = PHI [[t2LDRSH_PRE1]], %bb.3, %48, %bb.4
  ; CHECK-NEXT:   [[PHI1:%[0-9]+]]:rgpr = PHI [[COPY2]], %bb.3, %63, %bb.4
  ; CHECK-NEXT:   [[PHI2:%[0-9]+]]:gpr = PHI [[t2LDRSH_PRE1]], %bb.3, %48, %bb.4
  ; CHECK-NEXT:   [[PHI3:%[0-9]+]]:rgpr = PHI [[t2SDIV]], %bb.3, %53, %bb.4
  ; CHECK-NEXT:   t2STRHi12 [[PHI3]], [[PHI2]], 12, 14 /* CC::al */, $noreg :: (store (s16) into %ir.uglygep3, !tbaa !6)
  ; CHECK-NEXT:   [[t2LDRSH_PRE2:%[0-9]+]]:rgpr, [[t2LDRSH_PRE3:%[0-9]+]]:gpr = t2LDRSH_PRE [[PHI]], 16, 14 /* CC::al */, $noreg :: (load unknown-size from %ir.uglygep1, align 2, !tbaa !0)
  ; CHECK-NEXT:   [[t2LDRSHi12_1:%[0-9]+]]:rgpr = t2LDRSHi12 [[t2LDRSH_PRE3]], 2, 14 /* CC::al */, $noreg :: (load unknown-size from %ir.uglygep2, align 2, !tbaa !5)
  ; CHECK-NEXT:   [[t2LDRHi12_5:%[0-9]+]]:gprnopc = t2LDRHi12 [[t2LDRSH_PRE3]], 18, 14 /* CC::al */, $noreg :: (load unknown-size from %ir.uglygep9, align 2, !tbaa !5)
  ; CHECK-NEXT:   [[t2LDRHi12_6:%[0-9]+]]:gprnopc = t2LDRHi12 [[t2LDRSH_PRE3]], 8, 14 /* CC::al */, $noreg :: (load unknown-size from %ir.uglygep7, align 2, !tbaa !10)
  ; CHECK-NEXT:   [[t2LDRHi12_7:%[0-9]+]]:gprnopc = t2LDRHi12 [[t2LDRSH_PRE3]], 10, 14 /* CC::al */, $noreg :: (load unknown-size from %ir.uglygep8, align 2, !tbaa !11)
  ; CHECK-NEXT:   [[t2SDIV1:%[0-9]+]]:rgpr = t2SDIV [[t2LDRSH_PRE2]], [[t2LDRSHi12_1]], 14 /* CC::al */, $noreg
  ; CHECK-NEXT:   [[t2LDRHi12_8:%[0-9]+]]:gprnopc = t2LDRHi12 [[t2LDRSH_PRE3]], 4, 14 /* CC::al */, $noreg :: (load unknown-size from %ir.uglygep5, align 2, !tbaa !8)
  ; CHECK-NEXT:   [[t2MLS1:%[0-9]+]]:rgpr = t2MLS [[t2SDIV1]], [[t2LDRSHi12_1]], [[t2LDRSH_PRE2]], 14 /* CC::al */, $noreg
  ; CHECK-NEXT:   [[t2UXTH2:%[0-9]+]]:rgpr = t2UXTH [[t2SDIV1]], 0, 14 /* CC::al */, $noreg
  ; CHECK-NEXT:   [[t2LDRHi12_9:%[0-9]+]]:gprnopc = t2LDRHi12 [[t2LDRSH_PRE3]], 6, 14 /* CC::al */, $noreg :: (load unknown-size from %ir.uglygep6, align 2, !tbaa !9)
  ; CHECK-NEXT:   t2CMPrr [[t2LDRHi12_8]], [[t2UXTH2]], 14 /* CC::al */, $noreg, implicit-def $cpsr
  ; CHECK-NEXT:   [[t2UXTH3:%[0-9]+]]:rgpr = t2UXTH [[t2MLS1]], 0, 14 /* CC::al */, $noreg
  ; CHECK-NEXT:   [[t2ADDri4:%[0-9]+]]:rgpr = t2ADDri [[PHI1]], 1, 1 /* CC::ne */, $cpsr, $noreg, implicit [[PHI1]](tied-def 0)
  ; CHECK-NEXT:   t2CMPrr [[t2LDRHi12_9]], [[t2UXTH3]], 14 /* CC::al */, $noreg, implicit-def $cpsr
  ; CHECK-NEXT:   [[t2ADDri5:%[0-9]+]]:rgpr = t2ADDri [[t2ADDri4]], 1, 1 /* CC::ne */, $cpsr, $noreg, implicit [[t2ADDri4]](tied-def 0)
  ; CHECK-NEXT:   t2CMPrr [[t2LDRHi12_6]], [[t2UXTH2]], 14 /* CC::al */, $noreg, implicit-def $cpsr
  ; CHECK-NEXT:   [[t2ADDri6:%[0-9]+]]:rgpr = t2ADDri [[t2ADDri5]], 1, 1 /* CC::ne */, $cpsr, $noreg, implicit [[t2ADDri5]](tied-def 0)
  ; CHECK-NEXT:   t2CMPrr [[t2LDRHi12_7]], [[t2UXTH3]], 14 /* CC::al */, $noreg, implicit-def $cpsr
  ; CHECK-NEXT:   [[t2ADDri7:%[0-9]+]]:rgpr = t2ADDri [[t2ADDri6]], 1, 1 /* CC::ne */, $cpsr, $noreg, implicit [[t2ADDri6]](tied-def 0)
  ; CHECK-NEXT:   t2CMPri [[t2LDRHi12_5]], 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:gpr = COPY [[t2ADDri7]]
  ; CHECK-NEXT:   t2STRHi12 [[t2MLS1]], [[t2LDRSH_PRE3]], 14, 14 /* CC::al */, $noreg :: (store unknown-size into %ir.uglygep4, align 2, !tbaa !7)
  ; CHECK-NEXT:   t2Bcc %bb.4, 1 /* CC::ne */, $cpsr
  ; CHECK-NEXT:   t2B %bb.5, 14 /* CC::al */, $noreg
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.5:
  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[PHI4:%[0-9]+]]:gpr = PHI [[t2LDRSH_PRE1]], %bb.3, [[t2LDRSH_PRE3]], %bb.4
  ; CHECK-NEXT:   [[PHI5:%[0-9]+]]:rgpr = PHI [[t2SDIV]], %bb.3, [[t2SDIV1]], %bb.4
  ; CHECK-NEXT:   [[PHI6:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.3, [[COPY3]], %bb.4
  ; CHECK-NEXT:   t2STRHi12 [[PHI5]], [[PHI4]], 12, 14 /* CC::al */, $noreg :: (store unknown-size into %ir.uglygep3, align 2, !tbaa !6)
  ; CHECK-NEXT:   t2B %bb.2, 14 /* CC::al */, $noreg
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2.do.end:
  ; CHECK-NEXT:   $r0 = COPY [[PHI6]]
  ; CHECK-NEXT:   tBX_RET 14 /* CC::al */, $noreg, implicit $r0
  bb.0.entry:
    successors: %bb.1(0x80000000)

    %6:rgpr = t2MOVi32imm @bar
    %7:rgpr = t2SUBri killed %6, 16, 14 /* CC::al */, $noreg, $noreg
    %8:rgpr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
    %5:gpr = COPY %8
    %4:gpr = COPY %7

  bb.1.do.body:
    successors: %bb.2(0x04000000), %bb.1(0x7c000000)

    %0:gpr = PHI %4, %bb.0, %3, %bb.1
    %1:rgpr = PHI %5, %bb.0, %2, %bb.1
    %9:rgpr, %3:gpr = t2LDRSH_PRE %0, 16, 14 /* CC::al */, $noreg :: (load (s16) from %ir.uglygep1, !tbaa !0)
    %10:rgpr = t2LDRSHi12 %3, 2, 14 /* CC::al */, $noreg :: (load (s16) from %ir.uglygep2, !tbaa !5)
    %13:rgpr = t2SDIV %9, %10, 14 /* CC::al */, $noreg
    %14:rgpr = t2UXTH %13, 0, 14 /* CC::al */, $noreg
    t2STRHi12 %13, %3, 12, 14 /* CC::al */, $noreg :: (store (s16) into %ir.uglygep3, !tbaa !6)
    %15:rgpr = t2MLS %13, %10, %9, 14 /* CC::al */, $noreg
    %16:rgpr = t2UXTH %15, 0, 14 /* CC::al */, $noreg
    t2STRHi12 %15, %3, 14, 14 /* CC::al */, $noreg :: (store (s16) into %ir.uglygep4, !tbaa !7)
    %17:gprnopc = t2LDRHi12 %3, 4, 14 /* CC::al */, $noreg :: (load (s16) from %ir.uglygep5, !tbaa !8)
    t2CMPrr killed %17, %14, 14 /* CC::al */, $noreg, implicit-def $cpsr
    %19:rgpr = t2ADDri %1, 1, 1 /* CC::ne */, $cpsr, $noreg, implicit %1(tied-def 0)
    %20:gprnopc = t2LDRHi12 %3, 6, 14 /* CC::al */, $noreg :: (load (s16) from %ir.uglygep6, !tbaa !9)
    t2CMPrr killed %20, %16, 14 /* CC::al */, $noreg, implicit-def $cpsr
    %22:rgpr = t2ADDri %19, 1, 1 /* CC::ne */, $cpsr, $noreg, implicit %19(tied-def 0)
    %23:gprnopc = t2LDRHi12 %3, 8, 14 /* CC::al */, $noreg :: (load (s16) from %ir.uglygep7, !tbaa !10)
    t2CMPrr killed %23, %14, 14 /* CC::al */, $noreg, implicit-def $cpsr
    %25:rgpr = t2ADDri %22, 1, 1 /* CC::ne */, $cpsr, $noreg, implicit %22(tied-def 0)
    %26:gprnopc = t2LDRHi12 %3, 10, 14 /* CC::al */, $noreg :: (load (s16) from %ir.uglygep8, !tbaa !11)
    t2CMPrr killed %26, %16, 14 /* CC::al */, $noreg, implicit-def $cpsr
    %28:rgpr = t2ADDri %25, 1, 1 /* CC::ne */, $cpsr, $noreg, implicit %25(tied-def 0)
    %2:gpr = COPY %28
    %29:gprnopc = t2LDRHi12 %3, 18, 14 /* CC::al */, $noreg :: (load (s16) from %ir.uglygep9, !tbaa !5)
    t2CMPri killed %29, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
    t2Bcc %bb.1, 1 /* CC::ne */, $cpsr
    t2B %bb.2, 14 /* CC::al */, $noreg

  bb.2.do.end:
    $r0 = COPY %2
    tBX_RET 14 /* CC::al */, $noreg, implicit $r0

...
